Integrated circuits connect to and communicate with each other. Typically, integrated circuits communicate with each other by sending and receiving electronic signals via one or more electrical interconnects. Physically, the electrical interconnects comprise traces on a printed circuit board, wires or cables that connect between the integrated circuits. One or more such electrical interconnects may be referred to as a bus. Each of the integrated circuits may have an output driver circuit for driving electronic signals via the electrical interconnects to one or more receiver integrated circuits.
FIG. 1 illustrates one example of integrated circuits communicating with each other in a memory system. In FIG. 1, a bus 102 interconnects a memory controller 104 and memory modules 106. Each memory module 106 may include integrated circuits such as DRAMs. The memory controller and memory module each have one or more output drivers 108 that interface with the bus 102 for communicating electronic signals with other devices on the bus. The one or more output drivers of each memory module may be located, for example, in the one or more DRAMs. The speed of signal transmission via the bus 102 is a function of many factors such as the system clock speed, the amount of output current, the supply voltage, the number of loads on the bus, the impedance of the bus, the length of the bus, and the layout of the bus. The one or more conductors of the bus are sometimes referred to as channels. In some systems, all channels connect to a set of pull-up resistors R0 110 (one per channel, with just one being shown in FIG. 1).
Output drivers 108, such as is shown in FIG. 1, are preferably current mode drivers, which are designed to drive the bus 102 with an amount of current substantially independent of the supply voltage provided to the device. The output driver, however, preferably generates various drive capabilities in accordance with the load on the bus. For example, if the bus is heavily loaded with memory modules, the output driver preferably should generate a larger amount of current to drive a larger load. On the other hand, if the bus is lightly loaded, the output driver preferably should generate a smaller amount of current to drive a smaller load. FIG. 2 illustrates a prior art output driver 108 that drives one channel of the bus 102. The output driver 108 includes an output port 204 for connecting the output driver to the bus 102, a transistor 202 for driving the output port, a buffer 208 for driving the gate terminal of the transistor 202, a bias current source 216 and resistor 218 for providing a reference gate voltage 214, a gate capacitor 210 coupling to the reference voltage 214 for driving the buffer 208, and a data input 212. The drain terminal of the transistor 202 connects to the output port 204 and the source terminal of the transistor 202 connects to the circuit ground. The data input 212 is coupled to the input of the buffer 208 and the output of the buffer 208, node 206, is coupled to the gate terminal of the transistor 202. Node 206 controls the current drawn by transistor 202 from the bus 102.
One of the problems of the output driver illustrated in FIG. 2 is that the low threshold voltage transistor 202 may be damaged due to gate stress and electro-static discharge (ESD) caused by a large voltage swing on the bus. If a high threshold voltage transistor is used, a larger capacitor 210 is necessary to provide the power for driving the buffer 208.
Another problem with the output driver of FIG. 2 is that at the low internal voltage supply (e.g., 1.0 volts) used in many modern low power circuits, the output driver may not drive a sufficiently large voltage swing onto the bus 102.
Yet another problem with the output driver of FIG. 2 is that the internal impedance of the output driver is not adjustable. Without the capability to adjust the internal impedance, the output driver may not be able to account for the variation in topology, signal frequency, and other electrical characteristics of the bus in producing an optimal transmit signal when communicating with other devices on the bus.
Yet another problem with the output driver of FIG. 2 is that the internal impedance of the circuit is not controlled with respect to the frequency, power supply, process and temperature variations of the system.
In view of the shortcomings of the prior art, it is an objective to provide an output driver that can produce a large voltage swing on the bus with a low internal voltage supply. It is another objective to provide an output driver that can drive high frequency signals. It is another objective to provide an output driver that meets ESD and gate stress requirements. It is another objective to provide an output driver to which the internal impedance is adjustable, after completion of manufacturing, to optimize the signal quality required by the receiving device. It is another objective to provide an output driver that has an internal impedance that tracks the frequency, internal voltage, process and temperature variations of the system. More generally, it is an objective to provide an output driver with these characteristics.